Register for Pro Tune Up
Tuition is $695 for early registration and early payment.
Tuition is $745 for early registration and payment prior to class
Tuition is $795 for late registration and / or late payment.
Register for Pro Tune Up
Pro Tune Up 6 is a one day Signal Integrity, Power Integrity, and Electromagnetic Interference Control class that gives the student a well rounded explanation of proper high speed system design.
The purpose of the class is to teach the design methods and validation strategies necessary to assure first time success when implementing modern systems that would typically include, DDR3 / 4, SERDES, LVDS, Gigabit Ethernet, USB 1,2,3, Analog / Digital / RF, Switching Power Supplies, etc.
Pro Tune Up 5 is based on a design methodology developed by a major telecommunications company which has been documented over multiple years and thousands of designs to produce “right the first time” results 99% of the time. “Right the first time” means the systems work correctly at full speed, they are reliable, they have clearly defined manufacturing margins, and they are quiet enough to pass FCC & CISPR radiated emissions tests on the first try!
Target Audience: Electrical Engineers, FPGA Designers, EMC Certification Engineers and CAD Layout Designers responsible for implementing high speed digital and mixed analog digital systems.
The first 5 videos, Signal Integrity Analysis...the business case for doing it through Topology and Termination ... Introduction are mandatory pre-class homework for Pro Tune Up 5. The rest of the videos would be very helpful, but are not mandatory pre-class homework.
*** Mandatory Pre-class Homework for PTU 5 **
This is the first of 3 installments of this DDR3-2133 training video. This is a 1 hour 30 minute video. It goes through much of what I would explain in a pre-layout DDR3 consulting job. If you are going to do a DDR3 design please pay careful attention to the "principles" I am trying to explain. I have gotten involved with a number of DDR3 post layout validations that turned into Disaster Recovery jobs because my client had mis-understood the basics of high speed DDR3 design.
This is a post class lab and requires a password to view. The password was provided in the "Driving Instructions"
This lab was recorder using HyperLync 8.x. The lab works fine on HL 9.01 but the current display and the EMI display have not been implemented in 9.01.
According to my sources at Mentor the current display and EMI display will be worked back into the product at some time in the future.
Apparently the 9.x simulator is lightening fast, which is neat, but there is still work to be done on some of the nice, but lesser used features.