Pro Tune Up
The purpose of the class is to teach the design methods and validation strategies necessary to assure first time success when implementing modern systems that would typically include, DDR3 / 4, SERDES, LVDS, Gigabit Ethernet, USB 1,2,3, Analog / Digital, Switching Power Supplies, etc.
Pro Tune Up is based on a design methodology developed by a major telecommunications company which has been documented over multiple years and thousands of designs to produce “right the first time” results 99% of the time. “Right the first time” means the systems work correctly at full speed, they are reliable, they have clearly defined manufacturing margins, and they are quiet enough to pass FCC & CISPR radiated emissions tests on the first try!
Target Audience: Electrical Engineers, FPGA Designers, EMC Certification Engineers and CAD Layout Designers responsible for implementing high speed digital and mixed analog digital systems.
Basic Signal Integrity including board layer stack-up specification, high speed routing topology, space, trace, termination practices, and return current control. Get this wrong and the system will reward you with a host of problems including False Clock, False Data, Negative Timing Margins, Clock Jitter, Excessive EMI as well as a host of Manufacturing and Reliability issues.
Power Integrity is a lot more than one 0.1uF and two 0.01uF caps per pin. Power integrity depends upon stack-up, capacitor selection, placement, mounting technique, and quantity. Typical target impedance for memory systems must be around 0.1 ohm from DC to the highest frequency of interest. Poor design can result in power impedance poles and inter plane resonances. Many of the mysterious SI and EMI issues can be traced directly to poor power system design.
Root causes and cures for EMI. The goal is to stop the EMI noise at the source. If EMI noise is eliminated at the source, you do not need to chase it around the board. Once you have controlled the noise source, the next issue is to avoid making an efficient antenna. A noisy board with no antenna does not radiate. You need to clearly understand the key reasons for EMI if you want to have any chance of repeatable success.
DDR3 / DDR4 issues. Do you understand the four signal classes which make up a DDR3/4 memory interface. Do you know how to terminate and length match the signals in order to meet timing constraints. Do you know that most published length constraints are ridiculously tight. If you use SODIMM's, Master Clock, Address, Command, and Control need to be routed with VCC as the reference plane . Do you know why? What constitutes a "safe via?"
Differential Signaling What is the difference between 10/100 Base T Ethernet and LVDS? Are they fundamentally the same or is there a critical difference that can lead to other issues? With the huge noise margin available using LVDS devices, you can use almost any interconnect scheme. However, there can be other nasty complications like Cross Talk and EMI if you do it incorrectly.
SERDES interface routing issues … PCI Express, 10GHz XAUI, Gigabit Serial, etc.. We explain what is important and also debunk some of the popular myths about routing these types of interfaces. Do you understand how vias can cause a non-phase coherent channel?
Analog Digital Interface i.e. Isolation vs. Communication There are many ways you can do this, but only one is easy to understand and produces repeatably good results. How do you control EMI if you need to have long leads on isolated inputs?
Quiet DC to DC Switchers There are many voices in the technological wilderness. I teach a method that keeps these things from contaminating the rest of your design.
To Moat or Not To Moat..That is the question! Slicing up the ground plane has caused more problems than I can count. Do you know how to analyze these issues?
Proper Grounding Practice Can you explain how signal ground should be connected to chassis ground and why?
Connectors, Board to Board, Board to cable, etc. What are the SI, EMI, and Power Issues. When we get to the connector, we still need to deal with physics.
Basic Shielding & Filter Theory as it applies to Enclosures, Switching Power Supplies, and Renegade Chips
Critical elements in an effective high speed system design process. Simply performing a solid pre-layout design review and including the correct personnel can raise you first time odds of success to at least 65%. Adding the post-layout design review can result in first time success 90%+ even the first time you go through the process. Getting from 90% to 99% "right the first time" results is simply a matter of practice if you use methods based in real physics.
Teaching Method ...
The class is has three sections:
First: Pre-class home work videos. These are under the "Jump Start Tutorial" tab on the SIEMC.com web site.
Second: 7.5 hours of in class face to face training.
Third: 2 to 10 hours of post class hands on Signal Integrity and Power Integrity simulation labs. The post class labs are supported with videos of the instructor actually doing the lab, but the purpose is not to have the student mimic the instructor key stroke by key stroke. The purpose is to put the student into a known environment and then encourage them to explore the design space. The student needs to "twist the knobs" and get answers to questions specific to their own particular interests.
Using videos to cover the basics prior to class allows more time in class for advanced subjects . The pre-class videos are open to all whether or not you attend the class.
Post Class Labs. ...
Since we never have adequate time for all of the labs that would be useful, I have made an agreement with Mentor. If any student applies within two weeks of the time they take this class, they can get a temporary copy of the simulation software from Mentor. The labs, libraries, and instructional videos of me doing the labs can be down loaded from my website.
These labs are optional, but going through them can dramatically enhance the learning experience. Since the license is fully functional, this gives students the freedom to try their own examples.
Why should I attend this class?
Any Electrical Engineer, CAD Layout Designer, or Technical Manager who is tired of playing "Whack A Mole"** would find this class extremely useful. Students who have implemented this methodology have regularly produced complex designs that do indeed work correctly on the first implementation. This saves about $12,000 in out of pocket expenses and two-three months (calendar time) on the average project.
Is this class appropriate for a beginner? The pre-class homework material ( "Jump Start Tutorial" ) thoroughly covers the basics. In each class I also review the basics. Review of basics is mandatory because over 50% of problems I have found in Disaster Recovery Consulting has been directly related to basic structural errors. The laws of physics defines what happens electrically. You must go through the pre-class homework to be sure your opinions are based on real physics and not on some out of date application note.
Location & Tuition for Pro Tune Up 5
Pro Tune Up is offered through out North America as a public 1 day class which includes hands on labs using Mentor HyperLynx simulations tools.
( Note*** This is not a tool class. It is a high speed system design methods class and, as such, is equally appropriate regardless of your tool chain.***)
If you register 10 days in advance of class and present credit card payment or a valid PO 7 days in advance of the class, tuition is $695 USD.
If you register a 7 days prior to the class and pay before the class date, tuition is $745 USD.
Late registration and or late payment is $795 USD.
Cancellation or missed class policy.
Cancel 7 days in advance of the class --> full refund
Cancel less than 7 days in advance of the class but prior to class date --> 50% refund or free seat in the next class of your choice.
Cancel day of class or miss class --> no refund, but receive a free seat in the next class of your choice.
**For those of you who have not attended one of my previous classes, "Whack a Mole" is an arcade game that kids love. There are nine holes and a worm like creature ...a mole ...sticks its head up and the kids whack it with a plastic sledge hammer. After a few seconds the "mole" pops up in another location. The faster the kids whack the mole, the faster it moves to a new location. Kids love the game, but from a high speed design standpoint, it becomes an infuriating game quite rapidly. This class will help you permanently end the SI / EMI version of the "Whack A Mole" game.
Why do you bribe students to register early?
Early registration helps me guess at the level of interest in a particular location...ie the class size. Class size effects everything else.
A class of 20 students requires a much larger room, a bigger projector, a better screen, and more lab computers than a class of 5.
It is the pits to plan for 5 and then get a last minute registration for 10 more.
I need a proper size room for the class. If you are not comfortable, it will effect how well you learn.
Lab computers that travel with me are "carry on baggage." If I need more computers than I can carry, I need to ship them at least a week prior to the class. If I have two large classes back to back, I need to ship two sets of computers.
Occasionally the only practical way to solve the computer logistics is to have a few of the students bring their own computers to class. However, it takes about a ten days to get a temporary license for the simulation software. Hence planning ahead will make for a much happier instructor and a better experience for you the student.