Signal Integrity & EMC Process Implementation
Instructor Terry Fox BSEE Montana State University 1969
SIEMC Process Implementation is three days of face to face class room training including "hands on" Signal Integrity and Power Integrity simulation labs. This class includes much more information than that which is presented in the 1 day class. Lab exercise designs are a mix of pre-planned and "on the fly" student initiated designs. There is also a very popular "Stump the Professor" session. Present a design structure and find out whether or not there is a valid scientific reason to expect it to work reliably at full speed. Documents published in magazines and sample designs are normally considered to be reliable information. I have found them to range from very useful, to dubious, to highly detrimental. Implementing a design without understanding the physics behind the topology is very dangerous. I will explain which of these have a beneficial effect rooted in real science and which ones don't. We also address organizational process issues.
Key benefits of a design strategy based on the SIEMC Process Implementation:
1. Products function correctly at full speed on the first design build.
2. Products have a high manufacturing yield and a low warranty return rate.
3. The design cycle is predictable. This means, among other things, the products pass EMC regulatory requirements on the first attempt.
This class teaches organizations how to produce “right the first time” designs on a predictable and repeatable basis.
There are three main sections to this process.
1. Document the electrical requirements necessary for a fully functional system.
2. Develop the design rules necessary to insure you meet the electrical requirements.
3. Implement gating check points to assure the design is on track at each stage of development before moving forward.
Most of my consulting work is "Disaster Recovery." Companies call me in to save a project when it is four to six months late. Generally they have done three planned development board spins plus another two or three desperation board spins to “fix it.” The vast majority of the problems are conceptually simple, but the problems were “baked in” early in the design cycle.
Horribly late product development schedules are the result of a poor process focused on calendar dates rather than the quality of the intermediate work product. If you have a poor PCB layer stack-up or a bad floor plan, you need to catch that early in the cycle. If you get it wrong, you may not know that until you fail EMC tests just prior to the planned ship date.
This class illustrates an effective high speed digital system development process, the primary methods used to get critical answers, and the minimum check points necessary to verify you are on track.
SIEMC Process Implementation is based on a design methodology developed by a major telecommunications company which has been documented over multiple years and thousands of designs to produce “right the first time” results 99% of the time. “Right the first time” means the systems work correctly at full speed, they are reliable, they have clearly defined manufacturing margins, and they are quiet enough to pass FCC & CISPR radiated emissions tests on the first try!
Target Audience: Electrical Engineers, FPGA Designers, and CAD Layout Designers responsible for implementing high speed digital and mixed analog digital systems
Signal Integrity Signal Integrity including board layer stack-up specification, high speed routing topology, space, trace, termination practices, and return current control. Get this wrong and the system will reward you with a host of problems including False Clock, False Data, Negative Timing Margins, Clock Jitter, Excessive EMI as well as a host of Manufacturing and Reliability issues.
Power Integrity Power integrity depends upon stack-up, capacitor selection, placement, mounting technique, and quantity. Poor design can result in power impedance poles and inter plane resonances. Many of the mysterious SI and EMI issues can be traced directly to poor power system design.
Root Causes and Cures for EMI The goal is to stop the EMI noise at the source. If EMI noise is eliminated at the source, you do not need to chase it around the board. Once you have controlled the noise source, the next issue is to avoid making an efficient antenna. A noisy board with no antenna does not radiate. You need to clearly understand the key reasons for EMI if you want to have any chance of repeatable success.
DDR2 / DDR3 Issues Four signal classes make up a DDR2/3 memory interface. Some of the worst DDR2 and DDR3 implementations I have seen followed published guide lines. If you do a proper analysis, you will have a much easier implementation and far better noise margin.
Differential Signaling What is the difference between Ethernet 10/100 Base T and LVDS? With the huge noise margin available using LVDS devices, you can use almost any interconnect scheme. However there can be other nasty complications like Cross Talk and EMI if you do it incorrectly.
Giga Bit Serial - SERDES interface routing issues …PCI Express, 10GHz XAUI, etc.. We explain what is important and also debunk some of the popular myths about routing these types of interfaces. Do you understand how vias can cause a non-phase coherent channel?
Analog / Digital Interface Issues i.e. Isolation vs. Communication There are many ways you can do this, but only one is easy to understand and produces repeatedly good results. How do you control EMI if you need to have long leads on isolated inputs?
To Moat or Not to Moat Understanding the issues related to “quiet grounds" and the problem of signal ground vs. chassis ground. Moating the ground plane has caused more problems than I can count. Do you know why?
Connectors, Board to Board, Board to cable, etc. What are the SI, EMI, and Power Issues? When we get to the connector, we still need to deal with physics.
Grounding...how do you do it to avoid late design cycle issues?
Chip Level Package Issues We still need to deal with physics all the way to the actual die. In adequate power or orphaning the return current at the package will cause you design to fail.
The class also addresses Basic Shielding & Filter Theory, Effective Enclosures, Critical Switching Power Supply Issues, and spotting Renegade Chips
Teaching Method ...
The instructor will explain the problem and an appropriate method to solve that problem.
The instructor will demonstrate the solution using industry standard software tools.
The students will do the work for themselves using lab computers and sample problems.
In Class Pre-Layout Labs. ...
Multi Drop Topology & Termination
Power Plane Noise on 6 Layer Board vs 8 Layer Board
Power Delivery Impedance on 6 Layer Board vs 8 Layer Board
Signal Via Bypassing Using Capacitors vs Stitching Vias
DDR3 Design Example
In Class Post Layout Validation Labs …
Student Provided PC Boards which we will analyze in class.
Post Class Labs …
You will have 10 days to expand upon any of the in class labs … or you can invent your own. They key is to exercise what you have learned in class to lock in the knowledge.
About Terry Fox BSEE Montana State University 1969
After serving in the US Navy as a pilot and aircraft maintenance officer, Terry began his professional career in 1972 as a Hewlett Packard electronic instrument Field Engineer selling and supporting products ranging from DC to Microwave. During the Gate Array revolution of the mid 80’s Terry joined the Daisy team selling circuit simulation and physical design layout tools. In 1995 Terry began selling UniCAD Signal Integrity and EMC prediction tools on a commission only basis. After six months of no sales, Terry was ready to quit. UNICAD sent him a ticket to PCB West where he met the Director of PCB quality for Bell Northern Research and Northern Telecom, Stan Xavier. After a long conversation about a proper SIEMC design process, Terry realized he was in the wrong business. Terry was in the tool selling business when he should be in the solution providing business. Terry worked out a deal with UniCAD where he would sell services, UniCAD would back him up on the tough problems, and they would split the consulting fee. Since that time Terry has consulted on a great many projects. Each time the result has been the same. The product works at full speed and it passes regulatory tests on the first pass.
In 2004 Terry started offering public Signal Integrity and EMC classes throughout North America. He teaches 40 public classes and roughly 5-10 private classes each year in addition to his consulting practice. Terry has taught over 500 SI EMC classes to thousands of students and hundreds of companies always with the same message….build it right the first time…it is the best investment you can make.
( Note*** This is not a tool class. It is a high speed system design methods class and is equally appropriate regardless of your tool chain.***)